Fast opto isolators (like the ACSL6400, HCPL-263L, etc) have a max propagation delay specification of around 100nS. To pass say a UART signal through, it is easy to calculate the affect of the propagation delay on the signals. Actually for a single direction signal like a UART the propagation delay isn't too much of an issue at all if it is reasonably constant for the signal going high and going low as what comes out of the opto may be time shifted slightly but it will still be the same signal.
However with clocked buses such as SPI bus, etc, the propagation delay is much more significant if you are reading data back from a device on the opto isolated side (if the master SPI device is only sending data, e.g. writing to a DtoA IC, then actually it doesn't matter so much as for a UART). But for a full clocked bus comms link where you want to get data back based on the clock pulses, the max speed of the clock needs to be calculated as follows:
Working on the propagation delay above of 100ns for the opto isolators and a SPI bus.
We need to allow for the propagation delay in both directions, so 100nS for the clock to change on the way into the isolated side and 100nS for the signal to change on the way out. So 200nS. Now lets say we need a maximum of 80nS for the device to react to the clock (check this for your device) and then add say 40nS to ensure the signal has changed fully by the time the next clock edge occurs to be sure the signal read by the master will have fully changed in time at its pin (signals don't change instantly, especially out of opto outputs that need pull up resistors). This gives you a minimum of 320nS per clock edge possible. x2 for the high and low states of the clock and you get 640nS per complete clock cycle = 1.562MHz max clock speed possible.
You can't exceed this without finding faster opto isolators, so if fast speed is critical for your application ensure this doesn't catch you out.